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• DDR4 functionality and operations supported as defined in the component datasheet
• 288-pin,dual in-line memory module (UDIMM)
• Data transfer rates: 2666Mbps(max)
• 4GB, 8GB, 16GB
• VDD=1.20V(NOM)
• VPP=2.5V(NOM)
• VDDSPD=2.5V(NOM)
• Nominal and dynamic on-die termination(ODT) for data, strobe, and mask signals
• Low-power auto self refresh(LPASR)
• Data bus inversion(DBI) for data bus
• On-die VREFDQ generation and calibration
• On-board I 2C serial presence-detect(SPD) EEPROM
• 16 internal banks; 4 groups of 4 banks each
• Fixed burst chop(BC) of 4 and burst length(BL) of 8 via the mode register set(MRS)
• Selectable BC4 or BL8 on-the-fly (OTF)
• Gold edge contacts
• Halogen-free
• Fly-by topology
• Terminated control command and address bus
• Commercial(0°C≤ TOPER ≤ 85°C)
• 0.75ns@CL=19(DDR4-2666
• JEDEC standard 1.2V ± 0.06V Power Supply
• VDDQ = 1.2V ± 0.06V
• 800 MHz fCK for 1600Mb/sec/pin, 933 MHz fCK for 1866Mb/sec/pin, 1067MHz fCK for 2133Mb/sec/pin,1200MHz fCK for 2400Mb/sec/pin, 1333MHz fCK for 2666Mb/sec/pin
• 16 Banks (4 Bank Groups)
• Programmable CAS Latency: 10,11,12,13,14,15,16,17,18,19,20
• Programmable Additive Latency (Posted CAS): 0, CL - 2, or CL - 1 clock
• Programmable CAS Write Latency (CWL) = 9,11 (DDR4-1600), 10,12 (DDR4-1866), 11,14 (DDR4-2133),12,16 (DDR4-2400) and 14,18 (DDR4- 2666)
• Burst Length: 8, 4 with tCCD = 4 which does not allow seamless read or write [either On the fly using A12 or MRS]
• Bi-directional Differential Data Strobe
• On Die Terminati on using ODT pin
• Average Refresh Period 7.8us at lower then TCASE 85℃, 3.9us at 85°C < TOPER ≤ 95°C.
• Asynchronous Reset
